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16-Bit Long-Reach Video Automotive Grade SERDES with Bi-directional Side-Channel
ISL76321
The ISL76321 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bi-directionally over the same link during the video vertical retrace interval. I2C bus mastering allows the placement of external slave devices on the remote side of the link. An I2C controller can be placed on either side of the link allowing bidirectional I2C communication through the link to the external devices on the other side. Both chips can be fully configured from a single controller or independently by local controllers.
Features
* 16-bit RGB Transport Over a Single Differential Pair * 6MHz to 50MHz Pixel Clock Rates * AECQ100 Qualified Component * Bi-directional Auxiliary Data Transport Without Extra Bandwidth and Over the Same Differential Pair * Hot-plugging with Automatic Resynchronization Every HSYNC * I2C Bus Mastering to the Remote Side of the Link with a Controller on Either the Serializer or Deserializer * Selectable Clock Edge for Parallel Data Output * DC-balanced with Industry Standard 8b/10b Line Code Allows AC-coupling, Providing Immunity Against Ground Shifts * 16 Programmable Settings each for Transmitter Amplitude Boost and Pre-emphasis and Receiver Equalization, Allow for Longer Cable Lengths and Higher Data Rates * Slew Rate Control and Spread Spectrum Capability on Outputs Reduce the Potential for EMI * Same Device for Serializer and Deserializer Simplifies Inventory
Related Literature
* See FN6827, ISL34341 Data Sheet "WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel"
Applications
* Video Entertainment Systems * Remote Cameras
3.3V
1.8V VDD_IO
3.3V
1.8V VDD_IO
VDD_AN
VDD_IO
VDD_TX
VDD_P
VDD_CR
RSTB/PDB
RSTB/PDB
VDD_CDR
VDD_CDR
VDD_TX
VDD_AN
VDD_CR
VDD_IO
VDD_P
16
16 RGB
RGB
27nF 27nF
27nF SERIOP 27nF
VIDEO SOURCE
VSYNC HSYNC DE PCLK_IN
SERIOP
ISL76321 SERIALIZER
SERION REF_CLK
ISL76321 SERION DESERIALIZER
PCLK_IN GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO REF_RES TEST_EN
VSYNC HSYNC DE VIDEO_TX
VIDEO TARGET
PCLK_OUT
VIDEO_TX
GND_CR GND_AN GND_P GND_TX GND_CDR GND_IO
REF_RES
TEST_EN
I2CA1 I2CA0
3.16k
VDD_IO
FIGURE 1. TYPICAL APPLICATION
January 31, 2011 FN7803.0
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
3.16k
I2CA1 I2CA0
ISL76321 Block Diagram
SCL SDA I2C VCM GENERATOR RAM PREEMPHASIS 3 V/H /DE TDM RGB 16 RX EQ 8b/10b MUX DEMUX SERION SERIOP
TX
VIDEO_TX (HI ) CDR
PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO)
x20
PCLK_ OUT
x20
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ISL76321 Pin Configuration
ISL76321 (48 LD QFN) TOP VIEW
PCLK_OUT GND_IO GND_IO 37 36 VDD_CDR 35 GND_CDR 34 VDD_TX 33 SERIOP 32 SERION 31 GND_TX 30 VDD_AN 29 GND_AN 28 REF_RES 27 MASTER 26 I2CA0 25 I2CA1 13 GND_CR 14 VDD_CR 15 DATAEN 16 HSYNC 17 VSYNC 18 VHSYNCPOL 19 VIDEO_TX 20 PCLK_IN 21 GND_P 22 VDD_P 23 SCL 24 SDA VDD_IO 38
RGBA7
RGBA6
RGBA5
RGBA4
RGBA3
RGBA2
RGBA1 41
48 VDD_IO RGBC0 RGBC1 RGBC2 RGBC3 RGBC4 RGBC5 RGBC6 RGBC7 1 2 3 4 5 6 7 8 9
47
46
45
44
43
42
RGBA0 40
39
STATUS 10 TEST_EN 11 RSTB/PDB 12
Pin Descriptions
DESCRIPTION PIN NUMBER 47, 46 45, 44 43, 42 41, 40 9, 8 7, 6 5, 4 3, 2 16 17 15 20 39 33, 32 PIN NAME RGBA7, RGBA6 RGBA5, RGBA4 RGBA3, RGBA2 RGBA1, RGBA0 RGBC7, RGBC6 RGBC5, RGBC4 RGBC3, RGBC2 RGBC1, RGBC0 HSYNC VSYNC DATAEN PCLK_IN PCLK_OUT SERIOP, SERION SERIALIZER DESERIALIZER
Parallel video data LVCMOS inputs with Hysteresis Parallel video data LVCMOS outputs
Horizontal (line) Sync LVCMOS input with Hysteresis Horizontal (line) Sync LVCMOS output Vertical (frame) Sync LVCMOS input with Hysteresis Vertical (frame) Sync LVCMOS output Video Data Enable LVCMOS input with Hysteresis Pixel clock LVCMOS input Default; not used High-speed differential serial I/O Video Data Enable LVCMOS output PLL reference clock LVCMOS input Recovered clock LVCMOS output High speed differential serial I/O
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ISL76321 Pin Descriptions (Continued)
DESCRIPTION PIN NUMBER 18 PIN NAME VHSYNCPOL SERIALIZER CMOS input for HSYNC and VSYNC Polarity 1: HSYNC & VSYNC active low 0: HSYNC & VSYNC active high CMOS input for video flow direction 1: Video serializer 0: Video deserializer I2C Interface Pins (I2C DATA, I2C CLK), weak internal pull-up I2C Device Address I2C Master Mode 1: Master 0: Slave CMOS input for Reset and Power-down. For normal operation, this pin should be driven high. When this pin is taken low, the device will be reset. If this pin stays low, the device will be in PD mode. CMOS output for Receiver Status: 1: Valid 8b/10b data received 0: No valid data detected Note: serializer and deserializer switch roles during side-channel reverse traffic Analog bias setting resistor connection; use 3.16k 1% to ground PLL Ground Digital (Parallel and Control) Ground Analog (Serial) Data Recovery Ground Analog (Serial) Output Ground Analog Bias Ground Core Logic Ground Core Logic VDD Analog (Serial) Output VDD Analog Bias VDD Analog (Serial) Data Recovery VDD Digital (Parallel and Control) VDD PLL VDD Must be connected to ground Must be connected to ground, not an electrical connection DESERIALIZER
19
VIDEO_TX
24, 23 25, 26 27
SDA, SCL (Note 1) I2CA[1:0] (Note 1) MASTER
12 10
RSTB/PDB STATUS
28 21 37, 48 35 31 29 13 14 34 30 36 1, 38 22 11 Exposed Pad NOTES:
REF_RES GND_P (Note 2) GND_IO (Note 2) GND_CDR (Note 2) GND_TX (Note 2) GND_AN (Note 2) GND_CR (Note 2) VDD_CR VDD_TX VDD_AN VDD_CDR VDD_IO (Note 1) VDD_P TEST_EN PAD
1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components or features. 2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be considered a common connection.
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ISL76321 Ordering Information
PART NUMBER (Notes 3, 4, 5) ISL76321ARZ NOTES: 3. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL76321. For more information on MSL please see techbrief TB363. PART MARKING ISL76321 ARZ TEMP. RANGE (C) -40 to +105 48 Ld QFN PACKAGE (Pb-free) L48.7x7C PKG. DWG. #
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Absolute Maximum Ratings
Supply Voltage VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . -0.5V to 4.6V VDD_CDR to GND_CDR, VDD_CR to GND_CR . . . . . . . . . . . . . . . . -0.5V to 2.5V Between any pair of GND_P, GND_TX, GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V 3.3V Tolerant LVTTL/LVCMOS Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD_IO +0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Output Current . . . . . . . . . . . . . . . . . . . . Short Circuit Protected LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model (Tested per JESD22-A114E) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV SERIOP/N (All VDD Connected, all GND Connected) . . . . . . . . . . . . . . . . . . . . . . 8kV Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . 200V Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . 2000V Latch Up (Tested per JESD-78B; Class2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical) JA JC (C/W) QFN Package (Notes 6, 7) . . . . . . . . . . . . . . 32 3.7 Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-40C to +105C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 7. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating temperature range, -40C to +105C. PARAMETER SYMBOL CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS
Electrical Specifications
POWER SUPPLY VOLTAGE
VDD_CDR, VDD_CR VDD_TX, VDD_P, VDD_AN, VDD_IO 1.7 3.0 1.8 3.3 1.9 3.6 V V
SERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current Total 3.3V Supply Current PCLK_IN = 45MHz (Note 8) 62 40 80 52 mA mA
DESERIALIZER POWER SUPPLY CURRENTS
Total 1.8V Supply Current Total 3.3V Supply Current PCLK_IN = 45MHz (Note 8) 66 50 76 63 mA mA
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-Down Supply Current Total 3.3V Power-Down Supply Current RSTB = GND 10 0.5 mA mA
PARALLEL INTERFACE
High Level Input Voltage Low Level Input Voltage Input Leakage Current High Level Output Voltage Low Level Output Voltage Output Short Circuit Current VIH VIL IIN VOH VOL IOSC IOH = -4.0mA, VDD_IO = 3.0V IOL = 4.0mA, VDD_IO = 3.6V -1 2.6 0.4 35 0.01 2.0 0.8 1 V V A V V mA
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ISL76321
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating temperature range, -40C to +105C. (Continued) PARAMETER Output Rise and Fall Times SYMBOL tOR/tOF CONDITIONS Slew rate control set to min CL = 8pF Slew rate control set to max, CL = 8pF MIN (Note 10) TYP 1 4 MAX (Note 10) UNITS ns ns
Electrical Specifications
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency PCLK_IN Duty Cycle Parallel Input Setup Time Parallel Input Hold Time fIN tIDC tIS tIH 6 40 3.5 1.0 50 50 60 MHz % ns ns
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Frequency PCLK_OUT Duty Cycle PCLK_OUT Period Jitter (rms) PCLK_OUT Spread Width PCLK_OUT to Parallel Data Outputs (includes Sync and DE pins) Deserializer Output Latency fOUT tODC tOJ tOSPRD tDV tCPD Clock randomizer off Clock randomizer on Relative to PCLK_OUT, (Note 9) Inherent in the design -1.0 4 9 6 50 0.5 20 5.5 14 50 MHz % %tPCLK %tPCLK ns PCLK
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time REF_CLK to PCLK_OUT Maximum Frequency Offset tPLL PCLK_OUT is the recovered clock 1500 100 5000 s ppm
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit VODTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Differential Output Voltage, Non-Transition Bit VODNTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Generated Output Common Mode Voltage HS Common Mode Serializer-Deserializer Voltage Difference HS Differential Output Impedance HS Output Latency HS Output Rise and Fall Times HS Differential Skew HS Output Random Jitter HS Output Deterministic Jitter VOCM VCM ROUT tLPD tR/tF tSKEW tRJ tDJ PCLK_IN = 45MHz PCLK_IN = 45MHz Inherent in the design 20% to 80% 80 4 650 650 800 900 1100 1300 800 900 430 600 2.35 10 100 7 150 <10 6 25 20 120 10 900 900 mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P V mV PCLK ps ps psrms psP-P
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Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating temperature range, -40C to +105C. (Continued) PARAMETER SYMBOL CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS
Electrical Specifications
HIGH SPEED RECEIVER
HS Differential Input Voltage HS Generated Input Common Mode Voltage HS Differential Input Impedance HS Maximum Jitter Tolerance VID VICM RIN 80 75 2.32 100 0.50 120 mVP-P V UIP-P
I2 C
I2C Clock Rate (on SCL) I2C Clock Pulse Width (HI or LO) I2C Clock Low to Data Out Valid I2C Start/Stop Setup/Hold Time I2C Data in Setup Time I2C Data in Hold Time I2C Data out Hold Time NOTES: 8. IDDIO is nominally 50A and not included in this total as it is dominated by the loading of the parallel pins. 9. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is dependent on the PCLK frequency and is calculated as follows: 0.5 * fIN - tDV.. 10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. fI2C 1.3 0 0.6 100 100 100 1 100 400 kHz s s s ns ns ms
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ISL76321 Timing Diagrams
BIT BOUNDARY BIT BOUNDARY BIT BOUNDARY
TXP
Tx SETTING VOLTAGE 0x0F VCM 0x00 0xFF 0xF0
TXN
VOD TRANSITION BIT
VOD NON-TRANSITION BIT
FIGURE 2. VOD vs TX SETTING
SERIALIZER MODE
1/FIN PCLK_IN (RISING EDGE DEFAULT) tIS RGBA[7:0], RGBC[7:0] tIH VALID DATA DATA IGNORED DATA IGNORED tIS HSYNC OR VSYNC (HVSYNCPOL = `0') DATAEN (ACTIVE `1' DEFAULT) tIH VALID DATA tIDC
VALID DATA
FIGURE 3. PARALLEL VIDEO INPUT TIMING
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DESERIALIZER MODE
1/FOUT PCLK_OUT (RISING EDGE DEFAULT) tDV RGBA[7:0], RGBC[7:0] VALID DATA VALID DATA tDV HSYNC OR VSYNC ( HVSYNCPOL = `0') DATAEN (ACTIVE `1' DEFAULT) PREVIOUS DATA HELD VALID DATA tOR tOF tODC
FIGURE 4. PARALLEL VIDEO OUTPUT TIMING
Applications
Detailed Description and Operation
A pair of ISL76321 SERDES transports 16-bit parallel video for the ISL76321 along with auxiliary data over a single 100 differential cable either to a display or from a camera. Auxiliary data is transferred in both directions every video frame. This feature can be used for remote configuration and telemetry. The benefits include lower EMI, lower costs, greater reliability and space savings. The same device can be configured to be either a serializer or deserializer by setting one pin (VIDEO_TX), simplifying inventory. RGBA/C, VSYNC, HSYNC, and DATAEN pins are inputs in serializer mode and outputs in deserializer mode. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. The Side Channel data (auxiliary data) is transferred between the SERDES pair during the first two lines of the vertical video blanking interval. When the side-channel is enabled, which is the default, there will be a number of PCLK cycles uncertainty from frame-to-frame. This should not cause sync problems with most displays, as this occurs during the vertical front porch of the blanking period. When properly configured, the SERDES link supports end-to-end transport with fewer than one error in 1010 bits.
impedance, as well as the pre-emphasis and equalization settings. Functioning links of 25 meters are often possible at the maximum frequency. SERIOP and SERION pins incorporate internal differential termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode voltage difference and local power supply variations between two SERDES. The serializer outputs DC balanced 8b/10b line code, which allows AC-coupling. The AC-coupling capacitor on SERIO pins must be 27nF on the serializer board and 27nF on the deserializer board. The value of the AC-coupling capacitor is very critical since a value too small will attenuate the high-speed signal at a low clock rate. A value too big will slow down the turn around time for the side-channel. It is an advantage to have the pair of capacitors as closely matched as possible.
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into PCLK_IN pin. REF_CLK is used to recover the clock from the high-speed serial stream. REF_CLK is very sensitive to any instability. The following conditions must be met at all times after power is applied to the deserializer, or else the deserializer may need a manual reset: * VDD must be applied and stable * REF_CLK frequency must be within the limits specified * REF_CLK amplitude must be stable A simple 3.3V CMOS crystal oscillator can be used for REF_CLK
Differential Signals and Termination
The ISL76321 serializes the 16-bit parallel data plus 3 sync signals at 20x the PCLK_IN frequency. The extra 2 bits per word come from the 8b/10b encoding scheme which helps create the highest quality serial link. The high bit rate of the differential serial data requires special care in the layout of traces on PCBs, in the choice and assembly of connectors, and in the cables themselves. PCB traces need to be adjacent, matched in length and drawn to result in a differential 100 controlled impedance. For best EMI performance, the cable should be low loss and have a differential 100 impedance. The maximum cable length for a functioning link is dependent on the PCLK_IN frequency, the cable loss and 10
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at all times, including during power-up and power-down. To meet this requirement, the 3.3V supply must be powered up before the 1.8V supply. For the deserializer, REF_CLK must not be applied before the device is fully powered up. Applying REF_CLK before power-up
FN7803.0 January 31, 2011
ISL76321
may require the deserializer to be manually reset. A 10ms delay after the 1.8V supply is powered up guarantees normal operation.
120 10F 0.1F
Power Supply Bypassing and Layout
The serializer and deserializer functions rely on the stable functioning of PLLs locked to local reference sources or locked to an incoming signal. It is important that the various supplies (VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a wide range of frequencies, from below the typical loop bandwidth of the PLL to approaching the signal bit rate of the serial data. A combination of different values of capacitors from 1000pF to 5F or more with low ESR characteristics is generally required. The parallel LVCMOS VDD_IO supply is inherently less sensitive, but since the RGB and SYNC/DATAEN signals can all swing on the same clock edge, the current in these pins, and the corresponding GND pins, can undergo substantial current flow changes. Once again, a combination of different values of capacitors over a wide range, with low ESR characteristics, is desirable. A set of arrangements of this type is shown in Figure 5, where each supply is bypassed with a ferrite-bead-based choke, and a range of capacitors. A "choke" is preferable to an "inductor" in this application, since a high-Q inductor will be likely to cause one or more resonances with the shunt capacitors, potentially causing problems at or near those frequencies, while a "lossy" choke will reflect a high impedance over a wide frequency range. The higher value capacitor, in particular, needs to be chosen carefully, with special care regarding its ESR. Very good results can be obtained with multilayer ceramic capacitors (available from many suppliers) and generally in small outlines (such as the 1210 outline suggested in the schematic shown in Figure 5), which provide good bypass capabilities down to a few m at 1MHz to 2MHz. Other capacitor technologies may also be suitable (perhaps niobium oxide), but "classic" electrolytic capacitors frequently have ESR values of above 1, that nullify any decoupling effect above the 1kHz to 10kHz frequency range. Capacitors of 0.1F offer low impedance in the 10MHz to 20MHz region, and 1000pF capacitors in the 100MHz to 200MHz region. In general, one of the lower value capacitors should be used at each supply pin on the IC. Figure 5 shows the grounding of the various capacitors to the pin corresponding to the supply pin. Although all the ground supplies are tied together, the PCB layout should be arranged to emulate this arrangement (at least for the smaller value (high frequency) capacitors), as much as possible.
120
10F
0.1F
120 10F 0.1F
120 10F 0.1F
120 10F 0.1F
120 10F 0.1F
FIGURE 5. POWER SUPPLY BYPASSING
I2C Interface
The I2C interface allows access to internal registers used to configure the SERDES and to obtain status information. A serializer must be assigned a different address than its deserializer counterpart if the side channel is used. The upper 5 bits are permanently set to 011 11 and the lower 2 bits determined by pins as follows:
0 1 1 1 1 I2CA1 I2CA0 R/W
Thus, 4 SERDES can reside on the same bus. By convention, when all address pins are tied low, the device address is referred to as 0x78. SCL and SDA are open drain to allow multiple devices to share the bus. If not used, SCL and SDA should be tied to VDD_IO.
Side Channel Interface
The Side Channel is a mechanism for transferring data between the two chips on each end of the link. This data is transferred during video blanking so none of the video bandwidth is used. It has three basic uses: * Remote SERDES configuration * Data exchanges between two processors * Master Mode I2C commands to remote slaves This interface allows the user to initialize registers, control and monitor both SERDES chips from a single microcontroller which can reside on either side of the serial link. This feature is used to automatically transport the remote side SERDES chip's status back to a local register. The Side Channel needs to be enabled (the default) for this to work. In the case where there is a microcontroller on each side of the of the link, data can be buffered and exchanged between the two. Up to 224 bytes can be sent in each direction during each VSYNC active period.
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Master Mode
This is a mode activated by strapping the MASTER pin to a `1' on the ISL76321 on the remote side of the link from the microcontroller. This is a virtual extension of the I2C interface across the link that allows the local processor to read and write slave devices connected to the remote side SERDES I2C bus. No additional wires or components are needed other than the serial link. The I2C commands and data are transferred during video blanking causing no interruptions in the video data. In Master mode, the data is transported across the link by the Side Channel so the maximum throughput achievable would be the same. The SCL and SDA frequency is adjustable through the programming of a register. If a SERDES chip is configured as a master it is no longer available for communication by a local microcontroller. It is assumed that the SERDES is the only master.
Exposed Pad
While it is not a required electrical connection, it is recommended that the exposed pad on the bottom of the package be soldered to the circuit board. This will ensure that the full power dissipation of the package can be utilized. The pad should be connected to ground and not left floating. For best thermal conductivity, 16 vias should connect the footprint for the exposed pad on the circuit board to the ground plane. This connection is not required for basic operation of the chip.
COPPER PAD
VIAS 16x
FIGURE 6. LAYOUT FOR THE EXPOSED PAD
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ISL76321 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 1/31/11 REVISION FN7803.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL76321 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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Package Outline Drawing
L48.7x7C
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 0, 1/08
EXPOSED PAD AREA
7.00 6.75
48
A B
X
6.75 (48x 0.23) (48x 0.20) (48x 0.60)
Z
48 1
6 PIN 1 INDEX AREA
1
6 PIN #1 INDEX AREA
7.00
7.00 REF (4X)
(44X 0.50)
4
0.23
(4X)
0.15
(48X 0.40 0.1mm)
TOP VIEW
4.10 REF (4X)
0.100
CAB
BOTTOM VIEW
111 ALL AROUND
6.75
PACKAGE OUTLINE
Y
7.00 4.10 7.00 (44x 0.50)
SIDE VIEW
R0.200
0.450
C0.400X45X
(4X)
1
0.100 C
R0.200 MAX ALL AROUND
48 R0.115 TYP.
L
DETAIL "X"
DETAIL "Z"
0.65 0.85
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
0.19~ 0.245
SEATING
0.080 C
PLANE
2. Dimensioning and tolerancing conform to JESD-MO220. 3. Unless otherwise specified, tolerance : Decimal 0.05, body tolerance 0.1 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.28mm from the terminal tip. Frame base metal thickness 0.203mm. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
e b
0.100 0.050 CAB C
0.025 0.02
C
DETAIL "Y"
14
FN7803.0 January 31, 2011
(A LL
R0.200 TYP.
(0 .1
TYPICAL RECOMMENDED LAND PATTERN
AR 25 ) O U ND )

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